Design & Implementation

C/C++ modeling at the system and component level
Algorithm design and analysis (Matlab/Octave/SPW)
Verilog HDL design and simulation (Cadence & Synopsys)
Synthesis and behavioral synthesis (Synopsys)
Static timing analysis (Synopsys)
Detailed Verilog modeling of analog circuits and components
Formal verification (Synopsys)
FPGA implementation (Xilinx/Altera)

Magnetic finite-element analysis

Lab & Debug

Network analyzers & BERT
Protocol and logic analyzers
Spectrum analyzers and Audio Precision
FPGA prototyping

System & algorithms

Demodulators/Modems: QPSK/QAM/FSK/PSK/OFDM

Clock and symbol recovery: Digital PLL/phase detectors/analysis/8b10b/character sync
Digital filter design and signal identification
Fixed-point optimization with our own C++ library

Noise shaping: delta-sigma/psychoacoustic
Encryption and encoding
Channel modeling: ISI/fading/interferers/adjacent channel/noise

Deep audio and acoustics expertise

Standards & Protocols​

Zigbee HA1.2.1/PRO/IP

Bluetooth 2.0/1.1

PCI-Express 3.0/2.0

USB 3.0/2.0/1.1

SATA 3/2/1IEEE 1394B/A (Firewire